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CY62177EV30 MoBL(R)
32-Mbit (2 M x 16 / 4 M x 8) Static RAM
32-Mbit (2 M x 16 / 4 M x 8) Static RAM
Features

Functional Description
The CY62177EV30 is a high performance CMOS static RAM organized as 2 M words by 16 bits and 4 M words by 8 bits[1]. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery Life (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99 percent when addresses are not toggling. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written to the location specified on the address pins (A0 through A20). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. Pin #13 of the 48 TSOP I package is an DNU pin that must be left floating at all times to ensure proper application.
Thin small outline package (TSOP) I configurable as 2 M x 16 or as 4 M x 8 static RAM (SRAM) Very high speed 55 ns Wide voltage range 2.2 V to 3.7 V Ultra low standby power Typical standby current: 3 A Maximum standby current: 25 A Ultra low active power Typical active current: 4.5 mA at f = 1 MHz Easy memory expansion with CE1, CE2, and OE Features Automatic power down when deselected Complementary Metal Oxide Semiconductor (CMOS) for optimum speed and power Available in Pb-free 48-ball TSOP I package

Logic Block Diagram
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DATA IN DRIVERS
ROW DECODER
2M x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BYTE BHE WE OE BLE
CE2 CE1
Power-Down Circuit
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
BHE BLE
CE2 CE1
Note 1. For best practice recommendations, refer to the Cypress application note System Design Guidelines.
Cypress Semiconductor Corporation Document Number: 001-09880 Rev. *G
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 22, 2011
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Contents
Pin Configuration ............................................................. 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagram ............................................................ 12 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14
Document Number: 001-09880 Rev. *G
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CY62177EV30 MoBL(R)
Pin Configuration
Figure 1. 48-pin TSOP I (Forward) (2 M x 16 / 4 M x 8) [2, 3]
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE CE2 DNU BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE Vss I/O15/A21 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0
Product Portfolio
Power Dissipation Product VCC Range (V) Typ[4] 3.0 Speed (ns) Max 3.7 55 Typ[4] 4.5 Operating ICC (mA) f = 1 MHz Min CY62177EV30LL 2.2 Max 5.5 f = fMax Typ[4] 35 Max 45 Standby ISB2 (A) Typ[4] 3 Max 25
Notes 2. DNU Pin# 13 needs to be left floating to ensure proper application. 3. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 2 M x 16 SRAM. The 48-TSOP I package can also be used as a 4 M x 8 SRAM by tying the BYTE signal to VSS. In the 4 M x 8 configuration, Pin 45 is A21, while BHE, BLE, and I/O8 to I/O14 pins are not used. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C.
Document Number: 001-09880 Rev. *G
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ -65 C to +150 C Ambient temperature with power applied ........................................... -55 C to +125 C Supply voltage to ground potential ........................................ -0.3 V to VCC(max) + 0.3 V DC voltage applied to outputs in High Z state [5, 6] ....................... -0.3 V to VCC(max) + 0.3 V DC input voltage [5, 6] .................... -0.3 V to VCC(max) + 0.3 V Output current into outputs (LOW) ............................. 20 mA Static discharge voltage.......................................... > 2001 V (per MIL-STD-883, method 3015) Latch up current...................................................... > 200 mA
Operating Range
Device CY62177EV30LL Range Ambient Temperature VCC[7] Industrial -40 C to +85 C 2.2 V to 3.7 V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB2 [10, 11] Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input leakage current Output leakage current VCC operating supply current Automatic CE power down current--CMOS inputs Test Conditions IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.7 V VCC = 2.2 V to 2.7 V VCC= 2.7 V to 3.7 V GND < VI < VCC GND < VO < VCC, Output Disabled f = fMax = 1/tRC f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels VCC = 2.20 V VCC = 2.70 V VCC = 2.20 V VCC = 2.70 V 55 ns Min 2.0 2.4 - - 1.8 2.2 -0.3 -0.3 -1 -1 - - - Typ[8] - - - - - - - - - - 35 4.5 3 Max - - 0.4 0.4 VCC + 0.3 V VCC + 0.3 V 0.6 0.7[9] +1 +1 45 5.5 25 Unit V V V V V V V V A A mA mA A
CE1 > VCC - 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.7 V
Capacitance
Parameter[12] CIN COUT Description Input capacitance Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(typ) Max 15 15 Unit pF pF
Notes 5. VIL(min) = -2.0 V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 7. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 9. Under DC conditions the device meets a VIL of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7 V. 10. The BYTE pin in the 48-TSOP I package has to be tied to VCC to use the device as a 2 M x 16 SRAM. The 48-TSOP I package can also be used as a 4 M x 8 SRAM by tying the BYTE signal to VSS. In the 4 M x 8 configuration, Pin 45 is A21, while BHE, BLE, and I/O8 to I/O14 pins are not used. 11. Chip enables (CE1 and CE2) and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-09880 Rev. *G
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Thermal Resistance
Parameter[13] JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Figure 2. AC Test Loads and Waveforms VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R1 VCC GND R2 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Test Conditions Still air, soldered on a 3 x 4.5 inch, 2-layer printed circuit board TSOPI 44.66 12.12 Unit C/W C/W
Rise Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT OUTPUT RTH V
Table 1. AC Test Loads Parameter R1 R2 RTH VTH 2.5 V 16667 15385 8000 1.20 3.3 V 1103 1554 645 1.75 Unit V
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR
[15]
Description VCC for data retention Data retention current
Conditions VCC = 1.5 V, CE1 > VCC - 0.2 V or CE2 < 0.2 V, or (BHE and BLE) > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V
Min 1.5 -
Typ[14] - -
Max - 17
Unit V A
tCDR[13] tR[16]
Chip deselect to data retention time Operation recovery time Figure 3. Data Retention Waveform [17] VCC VCC(min) tCDR DATA RETENTION MODE VDR > 1.5 V
0 55
- -
- -
ns ns
VCC(min) tR
CE1 or BHE.BLE CE2
or
Notes 13. Tested initially and after any design or process changes that may affect these parameters. 14. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 15. Chip enables (CE1 and CE2) and Byte Enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 16. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 17. BHE.BLE is the AND of both BHE and BLE. Chip is deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-09880 Rev. *G
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Switching Characteristics
Over the Operating Range Parameter[18] Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[21]
Description
55 ns Min 55 - 6 - - 5 - 10 - 0 - - 10 - 55 40 40 0 0 40 40 25 0 - 10 Max - 55 - 55 25 - 18 - 18 - 55 55 - 18 - - - - - - - - - 20 -
Unit
Read cycle time Address to data valid Data hold from address change CE1 LOW and CE2 HIGH to data valid OE LOW to data valid OE LOW to LOW OE HIGH to High Z[19] Z[19, 20] Z[19, 20]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW and CE2 HIGH to Low Z[19] CE1 HIGH and CE2 LOW to High CE1 LOW and CE2 HIGH to power up CE1 HIGH and CE2 LOW to power down BLE/BHE LOW to data valid BLE/BHE LOW to Low Z
[19] [19, 20]
BLE/BHE HIGH to HIGH Z Write cycle time
CE1 LOW and CE2 HIGH to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width BLE/BHE LOW to write end Data setup to write end Data hold from Write End WE LOW to High WE HIGH to Low Z[19, 20] Z[19]
Notes 18. Test conditions for all parameters other than tristate parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in Table 1 on page 5. 19. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 21. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document Number: 001-09880 Rev. *G
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Switching Waveforms
Figure 4. Read Cycle 1 (Address Transition Controlled)[22, 23] tRC
ADDRESS
tOHA
DATA OUT
tAA DATA VALID
PREVIOUS DATA VALID Figure 5. Read Cycle 2 (OE Controlled)[23, 24]
ADDRESS
CE1
tRC tPD tACE tHZCE
CE2
BHE/BLE
tLZBE
OE
tDBE
tHZBE tHZOE
HIGH IMPEDANCE
DATA OUT VCC SUPPLY CURRENT
tLZOE HIGH IMPEDANCE tPU tLZCE
tDOE DATA VALID
50%
50%
ICC ISB
Notes 22. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. 23. WE is HIGH for read cycle. 24. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document Number: 001-09880 Rev. *G
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Switching Waveforms (continued)
Figure 6. Write Cycle 1 (WE Controlled) [25, 26, 27, 28]
tWC
ADDRESS
tSCE
CE1 CE2
tSA
WE
tAW
tPWE
tHA
BHE/BLE
tBW
OE
tSD
DATA I/O
tHD
NOTE 28
VALID DATA tHZOE
Figure 7. Write Cycle 2 (CE1 or CE2 Controlled) [25, 26, 27, 28] tWC
ADDRESS
tSCE
CE1 CE2
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE
tSD
DATA I/O NOTE 28
tHD
VALID DATA tHZOE
Notes 25. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. 26. Data I/O is high impedance if OE = VIH. 27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 28. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-09880 Rev. *G
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CY62177EV30 MoBL(R)
Switching Waveforms (continued)
Figure 8. Write Cycle 3 (WE Controlled, OE LOW)[29, 30] tWC
ADDRESS
tSCE
CE1
CE2
BHE/BLE
tBW tAW tHA
WE
tSA
tPWE
tSD
DATA I/O NOTE 30
tHD tLZWE
VALID DATA tHZWE
Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW)[29, 30] tWC
ADDRESS
CE1 CE2
tSCE tAW tHA tBW tSA
BHE/BLE
WE
tPWE tSD tHD
DATA I/O
NOTE 30
VALID DATA
Notes 29. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 30. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-09880 Rev. *G
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CY62177EV30 MoBL(R)
Truth Table
CE1 H X[31] X
[31]
CE2 X
[31]
WE X X X H H H L L L H H H
OE X X X L L L X X X H H H
BHE X
[31]
BLE X
[31]
Inputs Outputs High Z High Z High Z Data Out (I/O0-I/O15) High Z (I/O8-I/O15): Data Out (I/O0-I/O7) Data Out (I/O8-I/O15); High Z (I/O0-I/O7) Data In (I/O0-I/O15) High Z (I/O8-I/O15); Data In (I/O0-I/O7) Data In (I/O8-I/O15); High Z (I/O0-I/O7) High Z High Z High Z
Mode Deselect/Power Down Deselect/Power Down Deselect/Power Down Read Read Read Write Write Write Output Disabled Output Disabled Output Disabled
Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
L X
[31]
X[31] H L H L L H L L H L
X[31] H L L H L L H H L L
L L L L L L L L L
H H H H H H H H H
Note 31. The `X' (Don't care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 001-09880 Rev. *G
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CY62177EV30 MoBL(R)
Ordering Information
Speed (ns) 55 Ordering Code CY62177EV30LL-55ZXI Package Diagram 51-85183 Package Type 48-pin TSOP I (12 x 18.4 x 1 mm) Pb-free Operating Range Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 7 7 E V30 LL - 55 Z X I Temperature Grade: I = Industrial X = Pb-free Package Type: Z = 48-pin TSOP I Speed Grade: 55 ns Low Power Voltage Range: V30 = 3 V (typical) Process Technology: E = 90 nm Bus Width = x 16 Density = 32-Mbit 621 = MoBL SRAM family Company ID: CY = Cypress
Document Number: 001-09880 Rev. *G
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CY62177EV30 MoBL(R)
Package Diagram
Figure 10. 48-pin TSOP I (12 x 18.4 x 1 mm), 51-85183
51-85183 *B
Acronyms
Acronym CMOS I/O SRAM TSOP BHE BLE CE I/O OE WE input/output static random access memory thin small outline package byte high enable byte low enable chip enable input/output output enable write enable Description complementary metal oxide semiconductor
Document Conventions
Units of Measure
Symbol C MHz A mA ms ns % pF ps V W degree Celsius Mega Hertz micro Amperes milli Amperes milli seconds nano seconds ohms percent pico Farads pico seconds Volts Watts Unit of Measure
Document Number: 001-09880 Rev. *G
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CY62177EV30 MoBL(R)
Document History Page
Document Title: CY62177EV30 MoBL(R) 32-Mbit (2 M x 16 / 4 M x 8) Static RAM Document Number: 001-09880 Revision ** *A ECN 498562 2544845 Orig. of Change NXR VKN/PYRS Submission Date See ECN 07/29/08 Description of Change New Datasheet Removed 45 ns speed bin Added 70 ns speed bin Added 48-Pin TSOPI package Added footnote# 4 related to TSOPI package Added footnote# 9 related to ISB2 and ICCDR Updated Ordering information table Changed pin functions of pin# 10 from NC to A20 and pin# 13 from A20 to DNU in 48-Pin TSOPI package Replaced 70 ns speed with 55 ns Extended the VCC range to 3.7 V Changed ICC (max) spec from 2.8 mA to 4.5 mA at f = 1 MHz Changed ICC (max) spec from 30 mA to 45 mA at f = f(max) Removed ISB1 spec Changed ISB2 (max) spec from 17 A to 25 A Modified footnote #10 Converted from Preliminary to Final Changed ICC (max) spec from 4.5 mA to 5.5 mA at f = 1 MHz Changed ICC (typ) spec from 2.2 mA to 4.5 mA at f = 1 MHz Changed ICC (typ) spec from 28 mA to 35 mA at f = f(max) Added VIL spec for TSOP I package and footnote# 10 Changed COUT spec from 10 pF to 15 pF Included thermal specs Changed tOHA spec from 10ns to 6ns Removed inactive parts from Ordering Information. Updated Package Diagram Included BHE, BLE in footnote #11 Added footnote #25 related to chip enable Added Contents and Acronyms Updated links in Sales, Solutions, and Legal Information Updated Features (Removed FBGA package related information). Updated Pin Configuration (Removed FBGA package related information). Corrected NC to DNU in footnote #2 Updated Electrical Characteristics (Included BHE and BLE in ISB2 test conditions to reflect Byte power down feature). Updated Thermal Resistance (Removed FBGA package related information). Updated Data Retention Characteristics (Included BHE and BLE in ICCDR test conditions to reflect Byte power down feature). Added Ordering Code Definitions. Added Acronyms and Units of Measure. Removed FBGA package related information in all instances in the document. Updated in new template.
*B *C
2589750 2668432
VKN/PYRS VKN/PYRS
10/15/08 03/03/09
*D
2779867
VKN
10/06/09
*E *F
2899662 2927528
AJU VKN
03/26/10 05/04/2010
*G
3177000
AJU
02/18/2011
Document Number: 001-09880 Rev. *G
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
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(c) Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-09880 Rev. *G
Revised February 22, 2011
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MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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